--- orig_gcc.h	2015-05-25 13:27:12.426211329 +0530
+++ gcc.h	2015-05-25 13:25:02.934228392 +0530
@@ -139,10 +139,9 @@
 /* Compile read-write barrier */
 #define	WT_BARRIER() __asm__ volatile("" ::: "memory")
 
+#if defined(x86_64) || defined(__x86_64__)
 /* Pause instruction to prevent excess processor bus usage */
 #define	WT_PAUSE() __asm__ volatile("pause\n" ::: "memory")
-
-#if defined(x86_64) || defined(__x86_64__)
 #define	WT_FULL_BARRIER() do {						\
 	__asm__ volatile ("mfence" ::: "memory");			\
 } while (0)
@@ -152,7 +151,14 @@
 #define	WT_WRITE_BARRIER() do {						\
 	__asm__ volatile ("sfence" ::: "memory");			\
 } while (0)
-
+#elif defined(__PPC64__) || defined(PPC64)
+#define	WT_PAUSE() __asm__ volatile("ori 0,0,0" ::: "memory")
+#define WT_FULL_BARRIER() do {                                          \
+       __asm__ volatile ("sync" ::: "memory");                          \
+} while (0)
+#define WT_READ_BARRIER()      WT_FULL_BARRIER()
+#define WT_WRITE_BARRIER()     WT_FULL_BARRIER()
+  
 #elif defined(i386) || defined(__i386__)
 #define	WT_FULL_BARRIER() do {						\
 	__asm__ volatile ("lock; addl $0, 0(%%esp)" ::: "memory");	\