Create a skeleton implementation for the router synthesis stage, as defined in the technical design here.

The stage should let all non-control events through unmodified. It should fail when receiving topology control events, because these are never expected to reach the stage.

For change stream accounting control events, it should perform the per-transaction endOfTransaction accumulation as described in the technical design, i.e. if the event completes an existing transaction, it should emit a regular endOfTransaction change event and run it through an (optional) sub-pipeline with the user stages (if present on the change stream). The user stages can filter and transform the event.
If the event passes through, it needs to bump the ARM's PBRT to the resume token of the produced control event.

As a first step, add the basic infrastructure for the stage (DocumentSource, execution pipeline stage in exec::agg) and unit test it.