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  1. Core Server
  2. SERVER-24219

Make AlignedLockStats alignment respect platform specific cache lines

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    • Backwards Compatibility:
      Fully Compatible
    • Sprint:
      Platforms 2017-07-10

      Description

      Cache line sizes vary by platform, and specific processors.

      Processor Family Cache Line Size
      x64 64
      PowerPC64 128
      s390x 256

      For PowerPC64, I am considering POWER8 instead of older processors.

      An case where we try to align to cache line size: https://github.com/mongodb/mongo/blob/master/src/mongo/db/concurrency/lock_state.cpp#L90

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          depends on

          New Feature - A new feature of the product, which has yet to be developed. SERVER-29712 Polyfill std::hardware_{con,de}structive_interference_size

          • Major - P3 - Major loss of function.
          • Closed

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                  Updated:
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