On x86 (at least on intel) the story is a bit different. There, the crc32c instruction has a 3 cycle latency, but 3 can execute in parallel as long as they are independent, so the standard pattern is to do each chunk as 3 parallel streams and do a merge operation. See WT-2121 for some discussion. It may be worth reopening that and trying again since you are already set up to test it. You can find a BSD-or-GPL licensed implementation written by intel engineers linked to from that ticket, but to save you a hop, here you go.