We've recently renamed our READ/WRITE_BARRIER to ACQUIRE/RELEASE_BARRIERs in WT-12167 and WT-12170, but only made changes to the inline assembly for our supported architectures.

RISC-V is not a supported architecture, but the changes to fence instructions look like a quick win since the fences look like
    fence <instructions before>, <instructions after>
As an example the release barrier can become
    {{{}fence rw, w
{}}}which aligns with the definition of release semantics.

We should still review the RISC-V docs to check for any surprises, but strengthening these barriers is safe and aligns behaviour with our acquire/release macros