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  1. WiredTiger
  2. WT-2648

cache-line alignment for new ports

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    • Type: Icon: Improvement Improvement
    • Resolution: Done
    • Priority: Icon: Minor - P4 Minor - P4
    • WT2.9.0, 3.2.10, 3.3.11
    • Affects Version/s: None
    • Component/s: None
    • None

      WiredTiger currently sets the cache alignment target to 64 in hardware.h.

      According to david.daly, the Power8 port should be using 128 and the ZSeries should be using 256.

      mark.benvenuto, I think we're using #ifdef __powerpc64__ for the Power8, what's the right #ifdef for the ZSeries?

            Assignee:
            keith.bostic@mongodb.com Keith Bostic (Inactive)
            Reporter:
            keith.bostic@mongodb.com Keith Bostic (Inactive)
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              Created:
              Updated:
              Resolved: