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  1. WiredTiger
  2. WT-2648

cache-line alignment for new ports

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    Details

    • Type: Improvement
    • Status: Closed
    • Priority: Minor - P4
    • Resolution: Fixed
    • Affects Version/s: None
    • Fix Version/s: WT2.9.0, 3.2.10, 3.3.11
    • Component/s: None
    • Labels:
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      Description

      WiredTiger currently sets the cache alignment target to 64 in hardware.h.

      According to David Daly, the Power8 port should be using 128 and the ZSeries should be using 256.

      Mark Benvenuto, I think we're using #ifdef __powerpc64__ for the Power8, what's the right #ifdef for the ZSeries?

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            Assignee:
            keith.bostic Keith Bostic
            Reporter:
            keith.bostic Keith Bostic
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              Updated:
              Resolved: