Uploaded image for project: 'WiredTiger'
  1. WiredTiger
  2. WT-2648

cache-line alignment for new ports

    XMLWordPrintable

Details

    • Improvement
    • Status: Closed
    • Minor - P4
    • Resolution: Fixed
    • None
    • WT2.9.0, 3.2.10, 3.3.11
    • None
    • None

    Description

      WiredTiger currently sets the cache alignment target to 64 in hardware.h.

      According to david.daly, the Power8 port should be using 128 and the ZSeries should be using 256.

      mark.benvenuto, I think we're using #ifdef __powerpc64__ for the Power8, what's the right #ifdef for the ZSeries?

      Attachments

        Activity

          People

            keith.bostic@mongodb.com Keith Bostic
            keith.bostic@mongodb.com Keith Bostic
            Votes:
            0 Vote for this issue
            Watchers:
            2 Start watching this issue

            Dates

              Created:
              Updated:
              Resolved: