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  1. WiredTiger
  2. WT-5396

Review how WiredTiger uses WT_PUBLISH and WT_ORDERED_WRITE

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    • Type: Improvement
    • Status: Needs Scheduling
    • Priority: Major - P3
    • Resolution: Unresolved
    • Affects Version/s: None
    • Fix Version/s: None
    • Component/s: None
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      Description

      There has been some contention between Michael Cahill, Keith Bostic and Alexander Gorrod about when and how to control cases where it's important the order in which updates to different member variables are visible to other threads.

      A recent example of this was in WT-5119, where we added the WT_ORDERED_WRITE macro, which has the same semantic as WT_PUBLISH.

      Let's use this ticket to decide how to manage ordering in such cases, and be consistent moving forward.

      Some relevant content is in the Intel assembly documentation for sfence, which is how WT_PUBLISH is implemented. Specifically the section:

      The SFENCE instruction is ordered with respect to memory stores, other SFENCE instructions, MFENCE instructions, and any serializing instructions (such as the CPUID instruction). It is not ordered with respect to memory loads or the LFENCE instruction.

      We have some disagreement about whether an sfence implies that reads will also be ordered in respect to the sfence operation.

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              • Assignee:
                backlog-server-storage-engines Backlog - Storage Engines Team
                Reporter:
                alexander.gorrod Alexander Gorrod
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                • Created:
                  Updated: