WiredTiger requires the __atomic operations to provide a full barrier. That is not always the case, for instance, in the case of ARM64 platforms that do not have LSE atomic operations. This ticket will investigate the next steps for the non-LSE ARM64 platforms.
This is follow on work from
WT-8959 where we studied the implementation of the __atomic operations on the ARM platform.
We concluded that like x86_64, ARM64 with LSE atomics has a single instruction for CAS operation that is also a full memory barrier. We also realised that ARM64 platforms without the LSE atomics use load-acquire and store-release operations for atomic operations that do not equate to a full memory barrier that the WiredTiger requires.
WiredTiger abstracts out the platform-dependent atomic code using some macros. The usage of the macros assumes a full barrier and hence is incorrect on the non-LSE ARM platforms. These macros are frequently used in the concurrent code that is sensitive to both the performance and correctness.
Initiate a conversation with the stakeholders and come up with a solution and a timeline.