Change the ARM write barrier to be a dmb ishld + dmb ishst

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    • Type: Task
    • Resolution: Fixed
    • Priority: Major - P3
    • WT11.3.0, 8.0.0-rc0
    • Affects Version/s: None
    • Component/s: None
    • None
    • Storage Engines
    • 2024-02-20_A_near-death_puffin, 2024-03-05 - Claronald
    • 3

      We have confirmation from ARM that a those two barriers in combination are sufficient for release semantics, currently we have a full barrier.

      We will move to dmb ishld + dmb ishst.

            Assignee:
            Luke Pearson
            Reporter:
            Luke Pearson
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              Created:
              Updated:
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