I’ve noticed that our ACQ/REL barriers use different instructions than ones in GCC implementation, check whether it could be a bug.

GCC uses `dmb ish` for standalone acquire/release barriers, shouldn’t we switch to this barrier? Our code currently uses `dsb ishld ishst`.

The full history of ARM barriers changes for WT:

• https://github.com/wiredtiger/wiredtiger/pull/2075 - initial commit, just took implementation from some other product without explanation
• https://github.com/wiredtiger/wiredtiger/pull/6042 - change to dsb ishld ishst
• https://github.com/wiredtiger/wiredtiger/pull/7761 - weakening by switching from dsb to dmb
• https://github.com/wiredtiger/wiredtiger/pull/10045 - use full barrier for release + perf testing
• Basically that’s what compilers do (but here we did it for release only), no explanation why though

• https://jira.mongodb.org/browse/WT-12427 - Downgrade the arm release barrier to ishld, ishst together

The note in the ticket says that “We have confirmation from ARM that a those two barriers in combination are sufficient for release semantics, currently we have a full barrier.”

DoD: Understand why GCC uses different barriers and whether we need to use these ones as well