Priority: Major - P3
Affects Version/s: WT2.5.3, WT2.6.0
Fix Version/s: WT2.7.0
Environment:OS: Red Hat Enterprise Linux
WiredTiger gives MEMORY WRITE BARRIER issues with PPC.
This issue arises because there is no support for WT_WRITE_BARRIER, WT_READ_BARRIER and WT_FULL_BARRIER macros for PPC64. The macros are defined for Intel (mfence, sfence and lfence assembly instructions) but not for PPC64LE.
So, I have made a patch with which WiredTiger 2.6.0 builds successfully.
This patch applies to header file in path
1. The replacement for mfence and sfence Intel instructions is "sync" instruction for PPC64.
2. To avoid error related to "pause" instruction which is Intel instruction, I have copied it within Intel macro definitions and made a separate "WT_PAUSE" macro for PPC. The instruction "ORI" is called OR-Immediate and can be used as a NO-Operation by passing parameters "0,0,0". In documentation for PPC/Intel, it is mentioned that Pause can be replaced with No operation kind of behavior and hence the use of ORI
Though it builds, I am not sure how to test it for PPC64 and confirm that "sync" and "ori" does the job
Would appreciate your inputs on this patch.
Thanks in advance.